Double diffused MOS (DMOS) transistors are well known in the prior art. For example, U.S. Pat. No. 4,344,081, issued to Pao et al. on Aug. 10, 1982, which is incorporated herein by reference, shows one such prior art structure. FIG. 1 shows a cross section of a prior art N-channel DMOS power transistor. This prior art structure includes an N.sup.- epitaxial layer 11 formed on an N.sup.+ silicon substrate 10. Gate oxide layer 16 is formed on epitaxial layer 11 and doped polysilicon gate 15 is formed on oxide layer 16. Oxide layer 9 covers gate 15. P-type body regions 12a and 12b are diffused into epitaxial layer 11, and N.sup.+ source regions 13a and 13b are diffused into body regions 12a and 12b, respectively. Source regions 13a and 13b are electrically tied to body regions 12a and 12b by metal contacts 18 and 19, respectively. Contacts 18 and 19 are also electrically tied together. Regions 12c1 and 12c2 beneath gate 15 in body regions 12a and 12b, respectively, are channel regions. When the potential between gate 15 and source regions 13a and 13b is sufficiently high and with a positive voltage on drain contact 17, carriers flow laterally from source regions 13a and 13b through channel regions 12a and 12b, respectively, to drain region 11 and then vertically downward through drain region 11 and N.sup.+ substrate 10 to drain contact 17, as indicated by arrows 20a and 20b in FIG. 1. P-channel DMOS transistors have a similar structure, but P-type and N-type regions are reversed, and a voltage of the opposite sign produces current flow.
As explained above, the carriers that flow in the prior art vertical DMOS transistors shown in FIG. 1 must change direction, first flowing laterally and then vertically. Carrier flow is more efficient if the source, body and drain regions are arranged vertically as shown in FIG. 2. FIG. 2 shows a cross section of a prior art DMOS transistor with a U shaped gate extending into the epitaxial layer. This structure is due to Ueda et al. and is explained in more detail in A New Vertical Power MOSFET Structure with Extremely Reduced On-Resistance, by Ueda, et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-32, NO. 1, January 1985, which is incorporated herein by reference. In this prior art structure N.sup.- epitaxial layer 11 is again formed on N.sup.+ substrate 10. A P-type dopant is diffused into epitaxial layer 11 and an N.sup.+ -type dopant is diffused into a portion of the epitaxial layer that has been doped with a P-type dopant. Rectangular groove 23, having vertical walls, is then etched in the epitaxial layer using reactive ion beam etching, thereby creating P-type body regions 20a and 20b and corresponding N.sup.+ source regions 21a and 21b as shown in FIG. 2. Source regions 21a and 21b are electrically tied to body regions 20a and 20b, respectively, by metal contacts 18 and 19 which are also electrically tied together. A slight wet etch is then applied to smooth the surface of groove 23. Gate oxide 24 is formed in rectangular groove 23, and a U shaped polysilicon gate 25 is formed over gate oxide 24.
The prior art structure of FIG. 2 has the advantage that when the gate to source potential is sufficient to turn on the transistor, carriers flow vertically from N.sup.+ source regions 21a and 21b through channel regions 22c1 and 22c2 in body regions 20a and 20b, respectively, and continue to flow vertically downward through drain region 11 to N.sup.+ substrate 10 and drain contact 17. However, the structure of FIG. 2 has a disadvantage in that it is difficult to fabricate because it requires the formation of a U-shaped gate and results in a transistor with a nonplanar surface.